Imaging device

ABSTRACT

An imaging device is provided which can secure the dynamic range of a COMS imaging sensor, by storing a charge overflowing from a floating diffusion in a storage capacitance element and suppressing the increase of a pixel area which occurs if the storage capacitance element is formed by a MOS capacitor. The imaging device includes plural pixel circuits arranged in the row direction and the column direction, and plural storage capacitance lines arranged in the row direction and extending in the column direction. Each of the storage capacitance lines is coupled to the pixel circuits arranged in the same column. The pixel circuit includes a first photoelectric conversion element which stores a charge generated by being subjected to light, a floating diffusion to which the charge stored in the first photoelectric conversion element is transferred, and a first switching transistor coupling the floating diffusion and the storage capacitance line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation patent application of U.S. patentapplication Ser. No. 15/453,755 filed on Mar. 8, 2017 which is acontinuation patent application of U.S. patent application Ser. No.14/541,128 filed on Nov. 13, 2014, issued as U.S. Pat. No. 9,628,736 onApr. 18, 2017, which in turn claims the benefit of Japanese PatentApplication No. 2013-242956 filed on Nov. 25, 2013 including thespecification, drawings and Abstract are incorporated herein byreference in their entirety.

BACKGROUND

The present invention relates to an imaging device, for example, to animaging device of a CMOS (Complementary Metal-Oxide Semiconductor) type.

A CMOS imaging device, or the so-called COMS imaging sensor, has spreadwidely in the field of a digital camera. When expanding the applicationof the COMS imaging sensor to a vehicle-mounted camera or a surveillancecamera, enlargement of the dynamic range and also enhancement of theoperation speed are required.

Patent Document 1 and Patent Document 2 both disclose a solid-stateimaging device in which pixels are integrated in the shape of an array.Each of the pixels is configured with a photodiode which generates andstores a charge when subjected to light, a floating diffusion to whichthe charge stored in the photodiode is transferred, and a storagecapacitance element which stores a charge overflowing from the floatingdiffusion. Patent Document 3 discloses an imaging device in which pixelsare integrated in the shape of an array. In each of the pixels, fourphotodiodes are coupled to a gate of an amplification transistor viafour transfer transistors, respectively, and the output of theamplification transistor is fed externally via a select transistor.

Non Patent Literature 1 discloses a technology to enlarge the dynamicrange and a configuration of an image sensor in which a single slopeintegrating A/D converter is integrated.

Non Patent Literature 2 discloses a pixel circuit having a lateraloverflow integration capacitor (LOFIC) structure.

PATENT LITERATURE

-   (Patent Literature 1) Japanese Unexamined Patent Application    Publication No. 2005-328493-   (Patent Literature 2) Japanese Unexamined Patent Application    Publication No. 2006-217410-   (Patent Literature 3) Japanese Unexamined Patent Application    Publication No. 2010-212769

NON PATENT LITERATURE

-   (Non Patent Literature 1) “COMS image sensor”; Essential technology    series 9 of image information and television engineers, compiled by    Kiyoharu Aizawa and Takayuki Hamamoto, edited by Institute of Image    Information and Television Engineers, published by Corona Publishing    Co., Ltd., pp. 47, 159, and 174.-   (Non Patent Literature 2) “A Sensitivity and Linearity Improvement    of a 100-dB Dynamic Range CMOS Image Sensor Using a Lateral Overflow    Integration Capacitor”; Nana Akahane, Shigetoshi Sugawa, Satoru    Adachi, Kazuya Mori, Toshiyuki Ishiuchi, and Koichi Mizobuchi, IEEE    JOURNAL SOLID-STATE CIRCUITS, Vol. 41, No. 4, April 2006, pp.    851-858.

SUMMARY

A pixel of a COMS imaging sensor has secured the dynamic range, bytransferring a charge generated by a photodiode to a floating diffusionand by storing a charge overflowing from the floating diffusion in astorage capacitance element. When the capacity of the floating diffusionis set small in order to improve the sensitivity on the low illuminanceside, clipped whites will appear on the high illuminance side. On theother hand, when a storage capacitance element is formed in order tosuppress the appearance of clipped whites on the high illuminance side,the pixel area will increase and it will become difficult to realize alarge number of pixels. As in the pixel according to Patent Literature 1or Patent Literature 2, when a MOS capacitor is formed in asemiconductor substrate or over a semiconductor substrate as a storagecapacitance element, it becomes difficult to secure the area of aphotodiode. Furthermore, there is a disadvantage that high-k materialand a stacked capacitor push up the cost. The other issues and newfeatures of the present invention will become clear from the descriptionof the present specification and the accompanying drawings.

An imaging device according to one embodiment is configured with pluralpixel circuits arranged in the row direction and the column directionand plural storage capacitance lines arranged in the row direction andextending in the column direction. The storage capacitance lines arecoupled to the pixel circuits arranged in the same column. The pixelcircuit includes a first photoelectric conversion element which stores acharge generated by being subjected to light, a floating diffusion towhich the charge stored in the first photoelectric conversion element istransferred, and a first switching transistor which couples the floatingdiffusion and the storage capacitance line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of an imagingdevice according to Embodiment 1;

FIG. 2 is a circuit diagram of a pixel circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram of a column circuit illustrated in FIG. 1;

FIG. 4 is a timing chart explaining the read operation of the pixelcircuit illustrated in FIG. 2;

FIG. 5 is a potential chart at each time illustrated in FIG. 4;

FIG. 6 is a timing chart illustrating the read operation of the pixelcircuit by a single exposure in the column circuit illustrated in FIG.1;

FIG. 7 is a timing chart illustrating the read operation by doubleexposures in the column circuit illustrated in FIG. 1;

FIG. 8 is a block diagram illustrating a configuration of an imagingdevice according to Embodiment 2;

FIG. 9 is a circuit diagram of a column circuit illustrated in FIG. 8;

FIG. 10 is a timing chart illustrating the read operation of the pixelcircuit by a single exposure in the column circuit illustrated in FIG.9;

FIG. 11 is a block diagram illustrating a configuration of an imagingdevice according to Embodiment 3;

FIG. 12 is a circuit diagram of a pixel circuit illustrated in FIG. 11;

FIG. 13 is a timing chart explaining the read operation of the pixelcircuit illustrated in FIG. 12;

FIG. 14 is a block diagram illustrating a configuration of an imagingdevice according to Embodiment 4;

FIG. 15 is a circuit diagram illustrating the coupling relation of apixel circuit, a top reset transistor, and a bottom reset transistorillustrated in FIG. 14;

FIG. 16 is a timing chart explaining the read operation of the pixelcircuit illustrated in FIG. 15;

FIG. 17 is a block diagram illustrating a configuration of an imagingdevice according to Embodiment 5;

FIG. 18 is a circuit diagram illustrating the coupling relation of apixel circuit, a top reset transistor, and a bottom reset transistorillustrated in FIG. 17;

FIG. 19 is a timing chart explaining the read operation of the pixelcircuit illustrated in FIG. 18;

FIG. 20 is a block diagram illustrating a configuration of an imagingdevice according to Embodiment 6;

FIG. 21 is a circuit diagram of a pixel circuit illustrated in FIG. 20;and

FIG. 22 is a layout pattern of a pixel circuit illustrated in FIG. 21.

DETAILED DESCRIPTION

Hereinafter, the embodiments are explained with reference to thedrawings. When the number of elements, quantity, etc. are referred to inthe explanation of the embodiments, it is not always restricted to thenumber of elements, quantity, etc., unless otherwise described inparticular. In the drawings of the embodiments, the same referencesymbol and the same reference number shall express the same orcorresponding part. In the explanation of the embodiments, the repeatedexplanation will not be made in some cases to the same or correspondingpart to which the same reference symbol is attached.

Embodiment 1

FIG. 1 is a block diagram illustrating a configuration of an imagingdevice 100 according to Embodiment 1.

The imaging device 100 is configured with a pixel array 1, a verticalscanning circuit 2, a column circuit 31, and a constant current circuit4.

The pixel array 1 includes a pixel circuit PC1, a vertical signal lineVSL, and a storage capacitance line SCL. The pixel circuit PC1 isarranged in the shape of an array of (N+1) pieces in the row direction(the left and right direction in FIG. 1) and (M+1) pieces in the columndirection (the up and down direction in FIG. 1). For example, the symbol(x, n) attached to a rectangle pattern indicating a pixel circuit PC1expresses a pixel circuit located at the xth row and nth column, and thepixel circuit PC1 concerned is expressed as a PC1 (x, n) hereinafter.When the row number and the column number are not specified, the pixelcircuit is only expressed as a pixel circuit PC1.

The vertical signal line VSL extends in the column direction and (N+1)vertical signal lines are arranged in the row direction, with the samenumber as the number of the pixel circuits PC1. Hereinafter, thevertical signal line VSL coupled to the pixel circuit PC1 (x, n) isexpressed as a vertical signal line VSL (x). The storage capacitanceline SCL extends in the column direction and (N+1) storage capacitancelines are arranged in the row direction, with the same number as thenumber of the pixel circuits PC1. Hereinafter, the storage capacitanceline SCL coupled to the pixel circuit PC1 (x, n) is expressed as astorage capacitance line SCL (x). When there is no necessity ofreference specifying the row number x, they are simply expressed as avertical signal line VSL and a storage capacitance line SCL. A biascurrent is applied to each vertical signal line VSL by the constantcurrent circuit 4.

The vertical scanning circuit 2 outputs a row selection signal group R1(n) which selects one row of the pixel circuit PC1 from the plural rowsof the pixel circuit PC1. The row selection signal group R1 (n) selectsconcurrently the pixel circuit PC1 (0, n) to the pixel circuit PC1 (N,n) arranged at the nth row, among (M+1) rows of pixel circuits PC1arranged from the 0th row to the Mth row. (N+1) column circuits 31 arearranged in the row direction. Each column circuit 31 converts an analogsignal outputted by the corresponding vertical signal line VSL (x) intoa digital signal Dx, and outputs the digital signal Dx. The A/D(analog/digital) conversion in each column circuit 31 is concurrentlycontrolled by a column circuit control signal group CCTL31.

FIG. 2 is a circuit diagram of a pixel circuit PC1 illustrated in FIG.1.

(Configuration) The pixel circuit PC1 is configured with a photoelectricconversion element PD1, a transfer transistor MTX1, a floating diffusioncapacitor CFD, a reset transistor MRST1, an amplification transistorMAMI, a select transistor MSEL, a first switching transistor MSWA, and astorage line capacitor CM. A transfer transistor control signal TX1, areset transistor control signal RST1, a select transistor control signalSEL, and a first switching control signal SWA are applied to respectivegates of the transfer transistor MTX1, the reset transistor MRST1, theselect transistor MSEL, and the first switching transistor MSWA. Theabove-described row selection signal group R1 (n) is a bunch of thesefour control signals.

The photoelectric conversion element PD1 is an ordinary photodiodeformed over a semiconductor substrate (not shown). The power supplyvoltage GND is applied to an anode of the photoelectric conversionelement PD1. A cathode of the photoelectric conversion element PD1 iscoupled to one of a source and a drain of the transfer transistor MTX1.The other of the source and the drain of the transfer transistor MTX1 iscoupled to a drain of the reset transistor MRST1, and to one of a sourceand a drain of the first switching transistor MSWA. The power supplyvoltage VDD is applied to a source of the reset transistor MRST1. Theother of the source and the drain of the first switching transistor MSWAis coupled to a storage capacitance line SCL. A source and a drain ofthe select transistor MSEL are coupled to a drain of the amplificationtransistor MAMI and a vertical signal line VSL, respectively.

A storage line capacitor CM included in each pixel circuit PC1corresponds to the wiring capacitance of the storage capacitance lineSCL (x) passing through an area in which each pixel circuit PC1 isformed. That is, the value of the storage line capacitor CM correspondsto the value of the wiring capacitance of the entire storage capacitanceline SCL (x) divided by the number (M+1) of the pixel circuits PC1arranged in the column direction.

One terminal of the floating diffusion capacitor CFD is coupled to theother of the source and the drain of the transfer transistor MTX1, andthe other terminal of the floating diffusion capacitor CFD is appliedwith the power supply voltage GND. The floating diffusion capacitor CFDis an equivalent capacity of the floating diffusion (floating area)which converts a photo charge into a voltage. The floating diffusioncapacitor CFD includes the parasitic capacitance of an impuritydiffusion region and the parasitic capacitance of a wiring coupled tothe impurity diffusion region. The impurity diffusion region is formedindividually or separately to form the other of the source and the drainof the transfer transistor MTX1, the drain of the reset transistorMRST1, and one of the source and the drain of the first switchingtransistor MSWA.

(The operation) Upon being set in a conductive state by the resettransistor control signal RST1, the reset transistor MRST1 resets thefloating diffusion capacitor CFD. At this time, the storage linecapacitor CM is also concurrently reset by having set the firstswitching transistor MSWA in a conductive state by the first switchingcontrol signal SWA.

A photo charge stored in the photoelectric conversion element PD1 istransferred to the floating diffusion via the transfer transistor MTX1set in a conductive state, and the floating diffusion capacitor CFD ischarged. A charge overflowing from the floating diffusion is stored inthe storage line capacitor CM via the first switching transistor MSWAset in a conductive state. The amplification transistor MAMI amplifiesthe voltage of the floating diffusion capacitor CFD, and outputs it tothe vertical signal line VSL (x) via the select transistor MSEL.

FIG. 3 is a circuit diagram of the column circuit 31 illustrated inFIG. 1. The column circuit 31 converts an analog signal which the pixelcircuit PC1 (x, n) outputs via the vertical signal line VSL (x), into adigital signal Dx, and outputs the digital signal Dx. The column circuit31 is configured with a programmable gain amplifier PGA and an A/Dconverter circuit ADC. The A/D converter circuit ADC is a single slopeintegrating A/D converter circuit.

(The configuration and operation of the programmable gain amplifier PGA)The programmable gain amplifier PGA includes an input capacitor C1, afeedback capacitor C2, and a differential amplifier A1. The power supplyvoltage VDD1 and the power supply voltage GND1 are applied to thedifferential amplifier A1. A PGA reference voltage VRP is applied to apositive input terminal of the differential amplifier A1. One end of theinput capacitor C1 is coupled to the vertical signal line VSL, and theother end of the input capacitor C1 is coupled to a negative inputterminal of the differential amplifier A1.

The gain of the differential amplifier A1 is determined by the ratio ofthe value of the input capacitor C1 to the value of the feedbackcapacitor C2. The output signal of the pixel circuit PC1 applied to theone end of the input capacitor C1 is amplified by the differentialamplifier A1, and is outputted to the A/D converter circuit ADC as a PGAoutput signal POUT. It is also preferable to perform the gain adjustmentof the differential amplifier A1 by changing the value of the feedbackcapacitor C2 by the PGA gain setting signal GAIN, instead of changingthe value of the input capacitor C1 by the PGA gain setting signal GAIN.The gain of the differential amplifier A1 is generally set up by a DSP(digital signal processor) coupled in the latter stage of the columncircuit 31, based on the data of one frame period (refer to FIG. 4)outputted earlier.

(The configuration and operation of the A/D converter circuit ADC) TheA/D converter circuit ADC includes a capacitor C3, a capacitor C4, acomparator A2, a switch SW1, and a switch SW2. The power supply voltageVDD2 and the power supply voltage GND2 are applied to the comparator A2.

A PGA output signal POUT is applied to a positive input terminal AIN ofthe comparator A2 via the switch SW1. The conductive state of the switchSW1 is controlled by a sampling signal SMPL. Furthermore, one end of thecapacitor C3 is coupled to the positive input terminal AIN of thecomparator A2, and a ramp signal RAMP is applied to the other end of thecapacitor C3.

One end of the capacitor C4 is coupled to a negative input terminal ofthe comparator A2, and the power supply voltage GND2 is applied to theother end of the capacitor C4. Furthermore, the output of the comparatorA2 is applied to the negative input terminal of the comparator A2 viathe switch SW2. The conductive state of the switch SW2 is controlled byan auto-zero signal ATZ. Before applying the PGA output signal POUT tothe positive input terminal AIN of the comparator A2, the switch SW2 isset in a conductive state by the auto-zero signal ATZ to set a referencevoltage to the negative input terminal of the comparator A2. Thereby,the offset of the A/D converter circuit ADC is removed.

The switch SW1 is set in a conductive state for a predetermined timeafter the offset of the A/D converter circuit ADC is removed, and acharge corresponding to the voltage of the PGA output signal POUT isstored at the end of the capacitor C3 currently coupled to the positiveinput terminal AIN of the comparator A2. At this period, the voltage ofthe ramp signal RAMP applied to the other end of the capacitor C3 ismaintained on a prescribed level. Subsequently, the switch SW1 is set ina non-conductive state, the PGA output POUT is shifted to the highpotential side by the ramp signal RAMP, and it is swept with a certaingradient. When the voltage of the PGA output signal POUT shifted to thehigh potential side by the ramp signal RAMP becomes equal to thereference voltage set at the negative input terminal of the comparatorA2, the logical level of the output signal Dx of the A/D convertercircuit ADC is inverted.

By the above processing, the A/D converter circuit ADC converts the PGAoutput signal POUT into a pulse shape. The pulse shape is generated fromthe time when the PGA output POUT is shifted to the high potential sideby the ramp signal RAMP to the time when the PGA output POUT shifted tothe high potential side becomes equal to the reference voltage. The timeperiod when the pulse shape concerned is generated is measured with acounter (not shown in FIG. 3) and the count value is held; accordingly,the signal which the pixel circuit PC1 outputs is converted into adigital value.

FIG. 4 is a timing chart explaining the read operation of the pixelcircuit PC1 illustrated in FIG. 2. The timing chart of FIG. 4 isexplained referring to FIG. 2. FIG. 4 illustrates the timing chart inthe case of reading the data of the pixel circuit PC1 in a rollingshutter system with a single exposure. For the sake of simplification ofexplanation, it is assumed that as for the pixel array 1 (refer to FIG.1), the pixel circuits PC1 arranged (N+1) pieces per row are arranged intotal of 17 rows from the 0th row (Row 0) to the 16th row (Row 16).

As shown in the timing chart at the upper part of FIG. 4, one frameperiod spans from the data read start time of the pixel circuit PC1arranged at the 0th row (Row 0) to the data read completion time of thepixel circuit PC1 arranged at the 16th row (Row 16). At each row, areset period and a photoelectron storage period corresponding to theexposure time of the photoelectric conversion element PD1 arranged ateach row are set up before the read period of the pixel circuit PC1.

As shown in the waveform chart at the lower part of FIG. 4, at each readperiod starting after the end of the photoelectron storage period, eachrow of the pixel circuit PC1 is sequentially selected based on the rowselection signal group R1 outputted by the vertical scanning circuit 2.

At a read period TR (0), the vertical scanning circuit 2 selectsconcurrently the pixel circuit PC1 (0, 0) to the pixel circuit PC1 (N,0) arranged at the 0th row (Row 0) based on each control signal includedin the row selection signal group R1 (0). The output data of each pixelcircuit PC1 arranged at the 0th row is inputted into each correspondingcolumn circuit 31 via each pixel circuit PC1 and the vertical signalline VSL coupled thereto, respectively. Similarly in the followings, ateach of the read periods TR (1)-TR (16), the data of each pixel circuitPC1 arranged at the 1st row to the 16th row is read, respectively.

Hereinafter, the control operation of the pixel circuit PC1 by the rowselection signal group R1 (0) is explained in detail.

(Reset of the floating diffusion capacitor CFD and the storage linecapacitor CM) At time tRST, in response to the first switching controlsignal SWA set at a high level, the first switching transistor MSWA isset in a conductive state, and the floating diffusion capacitor CFD andthe storage line capacitor CM are coupled in parallel. Furthermore, inresponse to the reset transistor control signal RST1 set at a highlevel, the reset transistor MRST1 is set in a conductive state, and theresidual charge of the floating diffusion capacitor CFD and the storageline capacitor CM are discharged (reset). At this time, the transfertransistor MTX1 and the select transistor MSEL are set in anon-conductive state, on the basis of the transfer transistor controlsignal TX1 and the select transistor control signal SEL both set in alow level.

As illustrated in FIG. 4, at time tRST, in response to the firstswitching control signal SWA set at a low level, the first switchingtransistor MSWA included in the pixel circuit PC1 arranged at othernon-selected rows is set in a non-conductive state. That is, the storagecapacitance line SCL (x) is coupled to the first switching transistorMSWA included in the pixel circuit PC1 (x, 0) arranged at the 0th row,however, the storage capacitance line SCL (x) is not coupled to thefirst switching transistor MSWA included in the pixel circuit PC1arranged at other rows set as a non-selected row, such as the pixelcircuit PC1 (x, 1) arranged at the 1st row. Consequently, the resettransistor MRST1 included in the pixel circuit PC1 (x, 0) arranged atthe 0th row resets the floating diffusion capacitor CFD of the pixelcircuit PC1 (x, 0) and the storage line capacitor of the entire storagecapacitance line SCL (x).

On the other hand, the logical level of the reset transistor controlsignal RST1 of the non-selected row is maintained at a high level overthe read period TR (0). Consequently, the reset transistor MRST1 set ina conductive state maintains the reset of the floating diffusioncapacitor CFD included in each pixel circuit PC1 arranged at thenon-selected row.

(Read of a high-illuminance reset level) Between time tRST and time tHR,the logical level of the reset transistor control signal RST1 (0) isinverted from a high level to a low level, and the reset by the resettransistor MRST1 included in the pixel circuit PC1 arranged at the 0throw as the selected row is released. Originating in this reset release,a charge as a cause for a reset noise is stored in the floatingdiffusion capacitor CFD and the storage line capacitor CM which arecoupled in parallel by the first switching transistor MSWA. Hereinafter,this reset noise is also described as a “high-illuminance reset noise.”

As described above, the storage line capacitor CM included in the pixelcircuit PC1 arranged at the non-selected row is also coupled in parallelto the storage line capacitor CM included in the pixel circuit PC1arranged at the 0th row as the selected row. Therefore, a charge as acause for the reset noise is distributed to the floating diffusioncapacitor CFD and 17 storage line capacitors CM in total.

Furthermore, before time tHR, the logical level of the select transistorcontrol signal SEL (0) is also inverted from a low level to a highlevel, and the select transistor MSEL is set in a conductive state. Thehigh-illuminance reset noise is amplified by the amplificationtransistor MAMI, and is inputted into the column circuit 31 via theselect transistor MSEL and the vertical signal line VSL.

At time tHR, the programmable gain amplifier PGA included in the columncircuit 31 outputs the high-illuminance reset level, generated byamplifying the high-illuminance reset noise outputted by theamplification transistor MAMI, as the PGA output signal POUT.

(Read of a low-illuminance reset level) Before time tLR, the logicallevel of the first switching control signal SWA (0) is inverted from ahigh level to a low level, and the first switching transistor MSWA isset in a non-conductive state. As a result, the floating diffusioncapacitor CFD and the storage line capacitor CM which have been coupledin parallel are separated. The reset noise arising from this floatingdiffusion capacitor CFD is also described as a “low-illuminance resetnoise.” The low-illuminance reset noise is amplified by theamplification transistor MAMI, and is inputted into the column circuit31 via the select transistor MSEL and the vertical signal line VSL.

At time tLR, the programmable gain amplifier PGA included in the columncircuit 31 outputs the low-illuminance reset level, generated byamplifying the low-illuminance reset noise outputted by theamplification transistor MAMI, as the PGA output signal POUT.

(Photo charge transfer) At time tCT, the transfer transistor controlsignal TX1 (0) set at a low level generates a one shot pulse with aprescribed width. At this time, other control signals included in therow selection signal group R1 (0) hold the logical level at time tLR.Consequently, over the time when the transfer transistor control signalTX1 (0) is set at a high level, the photo charge stored in thephotoelectric conversion element PD1 is transferred to the floatingdiffusion capacitor CFD. The photo charge is stored only in the floatingdiffusion capacitor CFD at the time of the low illuminance. On the otherhand, at the time of the high illuminance, the photo charge is stored inthe floating diffusion capacitor CFD, and a charge overflowing from thefloating diffusion capacitor CFD is stored in the storage line capacitorCM.

(Read of a low-illuminance signal level) After the end of a one shotpulse generated at time tCT, the floating diffusion capacitor CFD storesa mixture of the charge as a cause for the low-illuminance reset noiseand the charge transferred from the photoelectric conversion elementPD1. The amplification transistor MAMI amplifies the voltage of thefloating diffusion capacitor CFD (hereinafter also described as a“low-illuminance mixed signal”), and outputs it to the column circuit 31via the select transistor MSEL and the vertical signal line VSL.

At time tLS, the programmable gain amplifier PGA included in the columncircuit 31 outputs the low-illuminance signal level, generated byamplifying the low-illuminance mixed signal outputted by theamplification transistor MAMI, as the PGA output signal POUT. When thephotoelectric conversion element PD1 is subjected to the light of a highilluminance, the low-illuminance signal level outputted at time tLS hasreached a saturation voltage.

(Read of a high-illuminance signal level) After a specified elapsed timefrom time tLS, the first switching control signal SWA (0) changes from alow level to a high level, and the first switching transistor MSWAcouples the floating diffusion capacitor CFD and the storage linecapacitor CM in parallel. The charge arising from the reset noise andstored in the floating diffusion capacitor CFD, the charge transferredfrom the photoelectric conversion element PD1, the charge arising fromthe reset noise and stored in the storage line capacitor CM, and thecharge overflowing from the floating diffusion capacitor CFD are storedin the floating diffusion capacitor CFD and the storage line capacitorCM which are coupled in parallel. The amplification transistor MAMIamplifies the voltage of the storage line capacitor CM and the floatingdiffusion capacitor CFD coupled in parallel (hereinafter also describedas a “high-illuminance mixed signal”), and outputs it to the columncircuit 31 via the select transistor MSEL and the vertical signal lineVSL.

At time tHS when the first switching control signal SWA (0) is set at ahigh level, the programmable gain amplifier PGA included in the columncircuit 31 outputs the high-illuminance signal level, generated byamplifying the high-illuminance mixed signal outputted by theamplification transistor MAMI, as the PGA output signal POUT.

(End of a read period TR (0)) After the completion of the read of thehigh-illuminance signal level, the logical level of the selecttransistor control signal SEL (0) is switched from a high level to a lowlevel, and the selection of the pixel circuit PC1 arranged at the 0throw is terminated. Subsequently, the logical level of the resettransistor control signal RST1 (0) is switched from a low level to ahigh level, and a charge stored in the floating diffusion capacitor CFDand the storage line capacitor CM is reset. Subsequently, the logicallevel of the first switching control signal SWA (0) is switched from ahigh level to a low level to set the first switching transistor MSWA ina non-conductive state, and each pixel circuit PC1 arranged at the 0throw is separated from each storage capacitance line CSL.

FIG. 5 is a potential chart at each time illustrated in FIG. 4. Theupper part (a) and the lower part (b) of FIG. 5 are potential chartswhen the photoelectric conversion element PD1 of the pixel circuit PC1is subjected to the light of a high illuminance, and the light of a lowilluminance, respectively. Here, “the light of a low illuminance”signifies the light of the illuminance of the degree to which the amountof the photo charge generated by the photoelectric conversion elementPD1 is enough to be stored in the floating diffusion capacitor CFD. “Thelight of a high illuminance” signifies the light of the illuminance ofthe degree to which the amount of the photo charge generated by thephotoelectric conversion element PD1 overflows from the floatingdiffusion capacitor CFD.

(In the case of a high illuminance) As illustrated in the upper part (a)of FIG. 5, after the end of the photoelectron storage period, at timetRST, the reset transistor MRST1 included in the pixel circuit PC1arranged at the selected row resets the floating diffusion capacitor CFDand the storage line capacitor CM which are coupled in parallel by thefirst switching transistor MSWA. Here, the storage line capacitor CM tobe reset includes the storage line capacitor CM in the non-selected row,in addition to the storage line capacitor CM in the selected row.

At time tHR, the read of the high-illuminance reset level is performed.The first switching transistor MSWA couples in parallel the floatingdiffusion capacitor CFD and the storage line capacitor CM, and the readof the “high-illuminance reset level” is performed.

At time tLR, the read of the low-illuminance reset level is performed.After canceling the parallel coupling of the floating diffusioncapacitor CFD and the storage line capacitor CM by the first switchingtransistor MSWA, the read of the “low-illuminance reset level” arisingfrom a charge stored in the floating diffusion capacitor CFD isperformed.

At time tCT, a photo charge transfer is performed. The transfertransistor MTX1 is set in a conductive state, and the photo chargestored in the photoelectric conversion element PD1 is transferred to thefloating diffusion capacitor CFD. A charge overflowing from the floatingdiffusion capacitor CFD is stored in the storage line capacitor CM.

At time tLS, the read of the low-illuminance signal level is performed.The amplification transistor MAMI amplifies the voltage of the floatingdiffusion capacitor CFD, and outputs it to the column circuit 31 via theselect transistor MSEL and the vertical signal line VSL. Theprogrammable gain amplifier PGA included in the column circuit outputsthe “low-illuminance signal level.” The upper part (a) of FIG. 5illustrates a state where the low-illuminance signal level is saturated,since the photoelectric conversion element PD1 is subjected to the lightof a high illuminance.

At time tHS, the read of the high-illuminance signal level is performed.The first switching transistor MSWA couples in parallel the floatingdiffusion capacitor CFD and the storage line capacitor CM. Theamplification transistor MAMI amplifies the voltage of the floatingdiffusion capacitor CFD and the storage line capacitor CM coupled inparallel, and outputs it to the column circuit 31 via the selecttransistor MSEL and the vertical signal line VSL. The programmable gainamplifier PGA included in the column circuit 31 outputs the“high-illuminance signal level.”

(In the case of a low illuminance) The lower part (b) of FIG. 5 is apotential chart at each time when the photoelectric conversion elementPD1 is subjected to the light of a low illuminance. The differencebetween the upper part (a) and the lower part (b) of FIG. 5 lies inwhether the photo charge overflows from the floating diffusion capacitorCFD (the upper part (a)) or does not overflow (the lower part (b)), intransferring the photo charge at time tCT. The difference originatesfrom the difference in the photo charge amount stored in thephotoelectric conversion element PD1 after the end of the photo chargestorage period, as illustrated in FIG. 5. The signal read operations attime tRST, time tHR, time tLR, time tCT, time tLS, and time tHS are thesame both in “the case of a high illuminance”, and “the case of a lowilluminance”; accordingly, the duplicated explanation thereof isomitted.

FIG. 6 is a timing chart illustrating the read operation of the pixelcircuit PC1 by a single exposure in the column circuit 31 illustrated inFIG. 1.

In FIG. 6, the horizontal axis expresses time and the vertical axisexpresses each signal wave form schematically. The vertical axis and thehorizontal axis are in an arbitrary scale.

Operation of the column circuit 31 illustrated in FIG. 6 is explainedwith reference to FIGS. 3 and 5. As described above, the column circuit31 (refer to FIG. 3) is configured with the programmable gain amplifierPGA and the A/D converter circuit ADC. The programmable gain amplifierPGA amplifies the voltage which is outputted by the amplificationtransistor MAMI of the pixel circuit PC1 and inputted via the verticalsignal line VSL, and generates the PGA output signal POUT.

(Digitization of a reset level) The A/D converter circuit ADC samplesand holds the high-illuminance reset level outputted by the programmablegain amplifier PGA in the capacitor C3 coupled to the positive inputterminal AIN, based on the sampling signal SMPL with a pulse width THR.At the hold time, the high-illuminance reset level is shifted to thehigh potential side by a ramp signal RAMP with a prescribed slope andcompared with the reference voltage VREF. In FIG. 6, a solid lineindicates the ramp signal RAMP, a dashed-dotted line indicates thereference voltage VREF, and a dashed line indicates the PGA outputsignal POUT. It is assumed that the high-illuminance reset level and thelow-illuminance reset level slightly exceed the value of the referencevoltage VREF. Therefore, the dashed lines to indicate both reset levelsare omitted in order to avoid the waveform chart becoming complicated.

The A/D converter circuit ADC outputs a high-illuminance digital resetsignal DHRx which has a time width from the time when the ramp signalRAMP starts a rise to the time when the high-illuminance reset levelshifted by the ramp signal RAMP becomes less than the reference voltageVREF. The last letter “x” in the signal name “DHRx” expresses that it isa high-illuminance digital reset signal of the pixel circuit PC1 (x, n)outputted to the vertical signal line VSL (x) arranged at the xth column(refer to FIG. 1).

The A/D converter circuit ADC generates a low-illuminance digital resetsignal DLRx following the generation of the high-illuminance digitalreset signal DHRx. The A/D converter circuit ADC samples and holds, inthe capacitor C3, the low-illuminance reset level outputted by theprogrammable gain amplifier PGA, based on the sampling signal SMPL witha one shot pulse of a pulse width TLR. At the hold time, thehigh-illuminance reset level is shifted to the high potential side by aramp signal RAMP and compared with the reference voltage VREF. The A/Dconverter circuit ADC outputs a low-illuminance digital reset signalDLRx which has a time width from the time when the ramp signal RAMPstarts a rise to the time when the low-illuminance reset level shiftedby the ramp signal RAMP becomes less than the reference voltage VREF.

(Digitization of a signal level) The A/D converter circuit ADC generatesa low-illuminance digital signal DLSx following the generation of thelow-illuminance digital reset signal DLRx. The A/D converter circuit ADCsamples and holds, in the capacitor C3, the low-illuminance signal leveloutputted by the programmable gain amplifier PGA, based on the samplingsignal SMPL with a one shot pulse of a pulse width TLS. At the holdtime, the low-illuminance signal level is shifted to the high potentialside by a ramp signal RAMP and compared with the reference voltage VREF.The A/D converter circuit ADC outputs a low-illuminance digital signalDLSx which has a time width from the time when the ramp signal RAMPstarts a rise to the time when the low-illuminance reset level shiftedby the ramp signal RAMP becomes less than the reference voltage VREF.

The A/D converter circuit ADC generates a high-illuminance digitalsignal DHSx following the generation of the low-illuminance digitalsignal DLSx. The A/D converter circuit ADC samples and holds, in thecapacitor C3, the high-illuminance signal level outputted by theprogrammable gain amplifier PGA, based on the sampling signal SMPL witha one shot pulse of a pulse width THS. At the hold time, thehigh-illuminance signal level is shifted to the high potential side by aramp signal RAMP and compared with the reference voltage VREF. The A/Dconverter circuit ADC outputs a high-illuminance digital signal DHSxwhich has a time width from the time when the ramp signal RAMP starts arise to the time when the high-illuminance reset level shifted by theramp signal RAMP becomes less than the reference voltage VREF.

(Extraction of a signal component) By the above processing, the A/Dconverter circuit ADC outputs the low-illuminance digital reset signalDLRx, the low-illuminance digital signal DLSx, the high-illuminancedigital reset signal DHRx, and the high-illuminance digital signal DHSx.The signal component for a low illuminance from which the reset noiseand the low frequency noise have been removed is extracted bycalculating the difference of the low-illuminance digital signal DLSxand the low-illuminance digital reset signal DLRx. Similarly, the signalcomponent for a high illuminance is extracted by calculating thedifference of the high-illuminance digital signal DHSx and thehigh-illuminance digital reset signal DHRx.

FIG. 7 is a timing chart illustrating the read operation by doubleexposures in the column circuit 31 illustrated in FIG. 1.

Differently from the rolling shutter system with a single exposureillustrated in FIG. 4, FIG. 7 illustrates the timing chart of therolling shutter system with double exposures as an example of therolling shutter system with multiple exposures. In the rolling shuttersystem with double exposures, a long time exposure (for a lowilluminance) and a short time exposure (for a high illuminance) areperformed in one frame period. As shown in the timing chart at the upperpart of FIG. 7, the photoelectron storage period in the long timeexposure is set up for a longer time than the photoelectron storageperiod in the short time exposure. It is also preferable to change theorder of the long time exposure and the short time exposure in theexposure sequence in one frame period. It is also preferable to control,independently and variably, the setup of the photoelectron storage timein the long time exposure and the short time exposure.

With reference to the waveform chart at the lower part of FIG. 7, thefollowing explains the read operation in each exposure period, in thecase of performing double exposures in the order illustrated in thetiming chart at the upper part of FIG. 7.

(Low-illuminance read period) At a low-illuminance read period, inresponse to the first switching control signal SWA set at a low level,the first switching transistor MSWA included in each of the pixelcircuits PC1 arranged from the 0th row (Row 0) to the 16th row (Row 16)is all set in a non-selected state. Consequently, in all the pixelcircuits PC1, the floating diffusion capacitor CFD is separated from thestorage line capacitor CM.

The floating diffusion capacitor CFD which has been reset by the resettransistor MRST1 is released from the reset by time tLR. Theamplification transistor MAMI amplifies the reset noise of the floatingdiffusion capacitor CFD. The amplified reset noise is inputted into thecolumn circuit 31 via the select transistor MSEL and the vertical signalline VSL.

At time tLR, the programmable gain amplifier PGA included in the columncircuit 31 outputs the low-illuminance reset level, generated byamplifying the reset noise outputted by the amplification transistorMAMI, as the PGA output signal POUT. When the read of thelow-illuminance reset noise is completed, in response to the one shotpulse of the transfer transistor control signal TX1, the photo chargestored in the photoelectric conversion element PD1 is transferred to thefloating diffusion capacitor CFD. The amplification transistor MAMIamplifies the voltage of the floating diffusion capacitor CFD in whichthe photo charge has been stored, and outputs it to the column circuit31.

At time tLS, the programmable gain amplifier PGA included in the columncircuit 31 outputs the low-illuminance signal level, generated byamplifying the signal outputted by the amplification transistor MAMI, asthe PGA output signal POUT. When the read of the low-illuminance resetlevel and low-illuminance signal level of the pixel circuit PC1 arrangedat the 0th row is completed, the read of the low-illuminance reset leveland low-illuminance signal level is performed sequentially up to thepixel circuit PC1 arranged at the last 16th row.

The A/D converter circuit ADC included in the column circuit 31 convertsthe low-illuminance reset level and the low-illuminance signal levelinto the low-illuminance digital reset signal DLR and thelow-illuminance digital signal DLS, respectively, and outputs them.

(High-illuminance read period) In the low-illuminance read period, thereset by the reset transistor MRST1 and the voltage amplified by theamplification transistor MAMI have been directed to the floatingdiffusion capacitor CFD. On the other hand, the reset and the voltageamplification in the high-illuminance read period is directed to thefloating diffusion capacitor CFD and the storage line capacitor CM whichare coupled in parallel by the first switching transistor MSWA.

The floating diffusion capacitor CFD and the storage line capacitor CMcoupled in parallel by the first switching transistor MSWA is reset andreleased from the reset by time tHR. The amplification transistor MAMIamplifies the reset noise of the floating diffusion capacitor CFD andthe storage line capacitor CM coupled in parallel, and outputs theamplified reset noise to the column circuit 31 via the select transistorMSEL and the vertical signal line VSL.

At time tHR, the programmable gain amplifier PGA included in the columncircuit 31 outputs the reset level, generated by amplifying the resetnoise outputted by the amplification transistor MAMI, as the PGA outputsignal POUT. When the read of the high-illuminance reset level iscompleted, in response to the one shot pulse of the transfer transistorcontrol signal TX1, the photo charge stored in the photoelectricconversion element PD1 is transferred to the floating diffusioncapacitor CFD and the storage line capacitor CM coupled in parallel. Theamplification transistor MAMI amplifies the voltage of the floatingdiffusion capacitor CFD in which the photo charge has been stored, andoutputs it to the column circuit 31.

At time tHS, the programmable gain amplifier PGA included in the columncircuit 31 outputs the high-illuminance signal level, generated byamplifying the signal outputted by the amplification transistor MAMI, asthe PGA output signal POUT. When the read of the high-illuminance resetlevel and the high-illuminance signal level of the pixel circuit PC1arranged at the 0th row is completed, the read of the high-illuminancereset level and high-illuminance signal level is performed sequentiallyup to the pixel circuit PC1 arranged at the last 16th row.

The A/D converter circuit ADC included in the column circuit 31 convertsthe high-illuminance reset level and the high-illuminance signal levelinto the high-illuminance digital reset signal DHR and thehigh-illuminance digital signal DHS, respectively, and outputs them.

The low-illuminance digital reset signal DLR, the low-illuminancedigital signal DLS, the high-illuminance digital reset signal DHR, andthe high-illuminance digital signal DHS are rendered to generate an HDRimaging (High Dynamic Range Imaging) by the digital signal processingcircuit in the latter stage of the column circuit 31, thereby it ispossible to obtain an image of a great dynamic range.

The effect of the imaging device 100 according to Embodiment 1 isexplained. The pixel circuit PC1 is configured with the photoelectricconversion element PD1, the floating diffusion capacitor CFD to which aphoto charge generated by the photoelectric conversion element PD1 istransferred, and the first switching transistor MSWA which controlscoupling between the floating diffusion capacitor and the storagecapacitance line SCL. The storage capacitance line SCL functions as thestorage line capacitor CM which stores a charge overflowing from thefloating diffusion capacitor, when reading a photo charge generated bythe photoelectric conversion element PD1.

A general pixel circuit adopts, in many cases, a MOS capacitor as acapacitor which stores a charge overflowing from the floating diffusioncapacitor. A MOS capacitor is formed at the interior of thesemiconductor substrate, or on the surface of the semiconductorsubstrate, as is the case with the photoelectric conversion element PD1.The MOS capacitor has a small value of capacitance per unit area andthere are area restrictions of the pixel circuit; therefore, it isdifficult to increase the capacitance value of the MOS capacitor. When astacked structure and high-k material are adopted instead of the MOScapacitor, there arises complication of the manufacturing process orcost increase due to the addition of new material.

On the other hand, the imaging device 100 according to Embodiment 1forms the storage capacitance line SCL not at the interior of nor on thesurface of the semiconductor substrate in which the photoelectricconversion element PD1 is formed, but with the use of the wiring layer.Consequently, provided that the pixel circuit has the same area, it ispossible to enlarge the area of the photoelectric conversion element,compared with the general pixel circuit. Furthermore, it is possible tosuppress the cost increase since ordinary manufacturing process andmaterial can be employed.

It is possible to secure the length of the storage capacitance line SCLto the extent of the length of the pixel circuit PC1 in the columndirection. When reading from the pixel circuit PC1, the storagecapacitance line SCL is coupled only to the pixel circuit PC1 arrangedat the selected column. Therefore, it is possible to store all thecharge which overflows from the floating diffusion capacitor.Consequently, it becomes possible to store the photo charge generated bythe photoelectric conversion element PD1 subjected to the light of ahigh illuminance, in the storage line capacitor CM, without increasingthe capacitance value of the floating diffusion capacitor. As a result,it is possible to realize the imaging device of a great dynamic range,maintaining the sensitivity on the low-illuminance side and suppressingthe appearance of clipped whites on the high-illuminance side.

Embodiment 2

FIG. 8 is a block diagram illustrating a configuration of an imagingdevice 200 according to Embodiment 2.

In FIG. 8, an element to which the same symbol as in FIG. 1 is attachedhas the same configuration or the same function, and the duplicatedexplanation thereof will be omitted. The imaging device 200 illustratedin FIG. 8 corresponds, in configuration, to the imaging device 100illustrated in FIG. 1 in which the column circuit 31 is replaced with acolumn circuit 32.

The imaging device 200 is configured with a pixel array 1, a verticalscanning circuit 2, a column circuit 32, and a constant current circuit4. (N+1) column circuits 32 are arranged in the row direction. Eachcolumn circuit 32 converts an analog signal outputted by thecorresponding vertical signal line VSL (x) into a digital signal Dx1 anda digital signal Dx2, and outputs them. The A/D (analog/digital)conversion in each column circuit 32 is concurrently performed by acolumn circuit control signal group CCTL32.

FIG. 9 is a circuit diagram of the column circuit 32 illustrated in FIG.8. The column circuit 32 is configured with a programmable gainamplifier PGA1, a programmable gain amplifier PGA2, an A/D convertercircuit ADC1, and an A/D converter circuit ADC2. The configuration andoperation of the programmable gain amplifiers PGA1 and PGA2 are the sameas those of the programmable gain amplifier PGA illustrated in FIG. 3.The configuration and operation of the A/D converter circuits ADC1 andADC2 are the same as those of the A/D converter circuit ADC illustratedin FIG. 3.

A vertical signal line VSL is coupled to one end of a switch SWCH andone end of a switch SWCL. The other end of the switch SWCH is coupled toone end of an input capacitor C1 of the programmable gain amplifierPGA1, and the other end of the switch SWCL is coupled to one end of aninput capacitor C1 of the programmable gain amplifier PGA2. Theopen/close states of the switch SWCH and the switch SWCL arecomplementarily controlled by a high-illuminance column selecting signalHSEL and a low-illuminance column selecting signal LSEL, respectively.

An output signal POUT1 of the programmable gain amplifier PGA1 isapplied to a positive input terminal AIN1 of the A/D converter circuitADC1 via a switch SWSH. An output signal POUT2 of the programmable gainamplifier PGA2 is applied to a positive input terminal AIN2 of the A/Dconverter circuit ADC2 via a switch SWSL. The open/close states of theswitch SWSH and the switch SWSL are controlled by a sampling signal SMPHand a sampling signal SMPL, respectively.

The A/D converter circuit ADC1 converts the signal applied to thepositive input terminal AIN1 into a digital signal Dx1 and outputs it.The A/D converter circuit ADC2 converts the signal applied to thepositive input terminal AIN2 into a digital signal Dx2 and outputs it.

FIG. 10 is a timing chart illustrating the read operation of the pixelcircuit PC1 by a single exposure in the column circuit 32 illustrated inFIG. 9.

In FIG. 10, the horizontal axis expresses time and the vertical axisexpresses each signal wave form schematically. The vertical axis and thehorizontal axis are in an arbitrary scale.

Operation of the column circuit 32 illustrated in FIG. 10 is explainedwith reference to FIGS. 5 and 9.

(Generation of a high illuminance digital reset signal DHRx and alow-illuminance digital reset signal DLRx) As illustrated in FIG. 5,after the reset of the floating diffusion capacitor CFD and the storageline capacitor CM, the amplification transistor MAMI of the pixelcircuit PC1 amplifies a high-illuminance reset noise and alow-illuminance reset noise, and outputs them to the vertical signalline VSL (x), sequentially.

As illustrated in FIG. 10, when a high-illuminance column selectingsignal HSEL is set at a high level and the low-illuminance columnselecting signal LSEL is set at a low level, the programmable gainamplifier PGA1 outputs the high-illuminance reset level, generated byamplifying the high-illuminance reset noise outputted by theamplification transistor MAMI, as the PGA output signal POUT1. Duringthe period when the programmable gain amplifier PGA1 outputs thehigh-illuminance reset level, the sampling signal SMPL is set at a lowlevel, and at the same time, the sampling signal SMPH is made togenerate a one shot pulse with a pulse width THR. Over the period of thepulse width THR, a high-illuminance reset level is applied to thepositive input terminal AIN1 of the A/D converter circuit ADC1 via theswitch SWSH. Even after the end of the one shot pulse of a pulse widthTHR, the high-illuminance reset level at the positive input terminalAIN1 of the A/D converter circuit ADC1 is held by the capacitor C3.

Subsequently, when the logical level of the high-illuminance columnselecting signal HSEL and the low-illuminance column selecting signalLSEL are inverted, the programmable gain amplifier PGA2 outputs thelow-illuminance reset level, generated by amplifying the low-illuminancereset noise outputted by the amplification transistor MAMI, as the PGAoutput signal POUT2. During the period when the programmable gainamplifier PGA2 outputs the low-illuminance reset level, the samplingsignal SMPH is set at a low level, and at the same time, the samplingsignal SMPL is made to generate a one shot pulse with a pulse width TLR.Over the period of the pulse width TLR, a low-illuminance reset level isapplied to the positive input terminal AIN2 of the A/D converter circuitADC2 via the switch SWSL. Even after the end of the sampling period TLR,the low-illuminance reset level at the positive input terminal AIN2 ofthe A/D converter circuit ADC2 is held by the capacitor C3.

When the high-illuminance reset level and the low-illuminance resetlevel are held respectively at the positive input terminal AIN1 of theA/D converter circuit ADC1 and at the positive input terminal AIN2 ofthe A/D converter circuit ADC2, a ramp signal RAMP is applied to theother end of the respective capacitor C3. The A/D converter circuit ADC1and the A/D converter circuit ADC2 output concurrently ahigh-illuminance digital reset signal DHRx and a low-illuminance digitalreset signal DLRx. The high-illuminance digital reset signal DHRx andthe low-illuminance digital reset signal DLRx have respectively a timewidth from the time when the ramp signal RAMP is applied concurrently tothe time when the high-illuminance reset level and the low-illuminancereset level which have been shifted to the high potential side by theramp signal RAMP become less than the reference voltage VREF.

As is the case with FIG. 6, it is assumed that the high-illuminancereset level and the low-illuminance reset level slightly exceed thevalue of the reference voltage VREF; therefore, dashed lines to indicateboth reset levels are omitted in order to avoid the waveform chartbecoming complicated.

(Generation of a high illuminance digital signal DHSx and alow-illuminance digital signal DLSx) As illustrated in FIG. 5, after anelapsed time tCT, the amplification transistor MAMI of the pixel circuitPC1 outputs a low-illuminance mixed signal and a high-illuminance mixedsignal to the vertical signal line VSL (x), sequentially.

As illustrated in FIG. 10, by maintaining the high-illuminance columnselecting signal HSEL at a low level and the low-illuminance columnselecting signal LSEL at a high level, the programmable gain amplifierPGA2 amplifies the low-illuminance mixed signal inputted via thevertical signal line VSL (x), and outputs a low-illuminance signal levelas the PGA output signal POUT2. During the period when the programmablegain amplifier PGA2 outputs the low-illuminance signal level, thesampling signal SMPH is set at a low level, and at the same time, thesampling signal SMPL is made to generate a one shot pulse with a pulsewidth TLS. Over the period of the sampling period TLS, a low-illuminancesignal level is applied to the positive input terminal AIN2 of the A/Dconverter circuit ADC2 via the switch SWSL. Even after the end of thesampling period TLS, the low-illuminance signal level at the positiveinput terminal AIN2 of the A/D converter circuit ADC2 is held by thecapacitor C3.

Subsequently, when the logical level of the high-illuminance columnselecting signal HSEL and the low-illuminance column selecting signalLSEL is inverted, the programmable gain amplifier PGA1 amplifies thehigh-illuminance mixed signal inputted via the vertical signal line VSL(x), and outputs a high-illuminance signal level as the PGA outputsignal POUT1. During the period when the programmable gain amplifierPGA1 outputs the high-illuminance signal level, the sampling signal SMPLis set at a low level, and at the same time, the sampling signal SMPH ismade to generate a one shot pulse with a pulse width THS. Over theperiod of the pulse width THS, a high-illuminance signal level isapplied to the positive input terminal AIN1 of the A/D converter circuitADC1 via the switch SWSH. Even after the end of the one shot pulse of apulse width THS, the high-illuminance signal level at the positive inputterminal AIN1 of the A/D converter circuit ADC1 is held by the capacitorC3.

When the low-illuminance signal level and the high-illuminance signallevel are held respectively at the positive input terminal AIN2 of theA/D converter circuit ADC2 and at the positive input terminal AIN1 andthe A/D converter circuit ADC1, a ramp signal RAMP is applied to theother end of the respective capacitor C3. The A/D converter circuit ADC2and the A/D converter circuit ADC1 output concurrently a low-illuminancedigital signal DLSx and a high-illuminance digital signal DHSx. Thelow-illuminance digital signal DLSx and the high-illuminance digitalsignal DHSx have respectively a time width from the time when the rampsignal RAMP is applied concurrently to the time when the low-illuminancesignal level and the high-illuminance signal level which have beenshifted to the high potential side by the ramp signal RAMP become lessthan the reference voltage VREF.

The effect of Embodiment 2 is explained by contrast with FIG. 6. Thecolumn circuit 32 is configured with the high-illuminance column circuit(the programmable gain amplifier PGA1 and the A/D converter circuitADC1) and the low-illuminance column circuit (the programmable gainamplifier PGA2 and the A/D converter circuit ADC2) arranged in parallelfor every column of the pixel circuit PC1, and the signal which isoutputted sequentially by the vertical signal line VSL is inputted intothe high-illuminance column circuit and the low-illuminance columncircuit sequentially by the multiplexer configured with the switch SWCHand the switch SWCL.

The programmable gain amplifier PGA1 included in the high-illuminancecolumn circuit and the programmable gain amplifier PGA2 included in thelow-illuminance column circuit amplify the signal outputted sequentiallyby the amplification transistor MAMI of the pixel circuit PC1 via thevertical signal line VSL, and generate the high-illuminance reset leveland the low-illuminance reset level. When the A/D converter circuit ADC1and the A/D converter circuit ADC2 hold the high-illuminance reset leveland the low-illuminance reset level at the input terminal respectively,the A/D converter circuit ADC1 and the A/D converter circuit ADC2perform the A/D conversion concurrently.

As for the processing time of the column circuit 32, the A/D convertercircuit ADC1 and the A/D converter circuit ADC2 are dominant. Inparticular, when the amplitude of the signal inputted into the A/Dconverter circuit ADC1 and the A/D converter circuit ADC2 becomes large,the increase in the processing time of the column circuit 32 is moreremarkable. Even when the input signal of such large amplitude isprocessed, the processing time of the column circuit 32 is settled justover or below 40% of the processing time of the column circuit 31illustrated in FIG. 6, by operating the A/D converter circuit ADC1 andthe A/D converter circuit ADC2 concurrently. As a result, it is possibleto enhance the speed of the image processing capability of the imagingdevice 200, by the speed enhancement of the column circuit 32.

Embodiment 3

FIG. 11 is a block diagram illustrating a configuration of the imagingdevice 300 according to Embodiment 3.

In FIG. 11, an element to which the same symbol as in FIG. 1 is attachedhas the same configuration or the same function, and the duplicatedexplanation thereof will be omitted. The imaging device illustrated inFIG. 11 corresponds, in configuration, to the imaging device 100illustrated in FIG. 1 in which the pixel array 1 is replaced with apixel array 13 and the vertical scanning circuit 2 is replaced with avertical scanning circuit 23.

The imaging device 300 is configured with a pixel array 13, a verticalscanning circuit 23, a column circuit 31, and a constant current circuit4.

The pixel array 13 includes a pixel circuit PC3, a vertical signal lineVSL, and a storage capacitance line SCL3. The pixel circuit PC3 isarranged in the shape of an array of (N+1) pieces in the row directionand (M+1) pieces in the column direction. The vertical signal line VSLextends in the column direction, and (N+1) vertical signal lines arearranged in the row direction, with the same number as the number of thepixel circuits PC3. The storage capacitance line SCL3 extends in thecolumn direction and (N+1) storage capacitance lines are arranged in therow direction, with the same number as the number of the pixel circuitsPC3. A bias current is applied to each vertical signal line VSL by theconstant current circuit 4.

The vertical scanning circuit 23 outputs a row selection signal group R3(n) which selects one row of the pixel circuit PC3 from the plural rowsof the pixel circuit PC3. As is the case with Embodiment 1, each columncircuit 31 converts an analog signal outputted by the correspondingvertical signal line VSL (x) into a digital signal Dx, and outputs thedigital signal Dx. The A/D (analog/digital) conversion in each columncircuit 31 is concurrently controlled by a column circuit control signalgroup CCTL31.

FIG. 12 is a circuit diagram of a pixel circuit PC3 illustrated in FIG.11. The pixel circuit PC3 corresponds, in configuration, to the pixelcircuit PC1 illustrated in FIG. 2 in which a second switching transistorMSWB and a unit storage capacitance line USCL are added. Accordingly,the row selection signal group R3 (n) for selecting the pixel circuitPC3 (x, n) arranged at the nth row is configured by adding the secondswitching control signal SWB (n) for controlling the conductive state ofthe second switching transistor MSWB, to the row selection signal groupR1 (n) illustrated in FIG. 1. The unit storage capacitance line USCLcorresponds to a portion of the storage capacitance line SCL (x) whichis included in the pixel circuit PC3 (x, n).

In the pixel circuit PC3 (x, n), one of a source and a drain of thefirst switching transistor MSWA is coupled to the unit storagecapacitance line USCL. A source of the second switching transistor MSWBis coupled to one end of the unit storage capacitance line USCL. A drainof the second switching transistor MSWB is coupled to the other end ofthe unit storage capacitance line USCL included in the pixel circuit PC3(x, n−1). The other end of the unit storage capacitance line USCLincluded in the pixel circuit PC3 (x, n) is coupled to a drain of thesecond switching transistor MSWB included in the pixel circuit PC3 (x,n+1).

FIG. 13 is a timing chart explaining the read operation of the pixelcircuit PC3 illustrated in FIG. 12. The timing chart illustrated in FIG.13 is explained referring to FIG. 12. As is the case with FIG. 4, FIG.13 illustrates the timing chart in the case of reading the data of thepixel circuit PC3 in a rolling shutter system with a single exposure.

In FIG. 13, the read period TR (n−1), the read period TR (n), and theread period TR (n+1) indicate the read period of the pixel circuit PC3arranged at the (n−1) th row, the nth row, and the (n+1) th row,respectively. The following explains the read timing of the pixelcircuit PC3 (x, n) arranged at the nth row.

Just before the read period TR (n−1) from time t0 to time t1 ends, thefirst switching control signal SWA (n−1), the second switching controlsignal SWB (n−1), the reset transistor control signal RST1 (n−1), andthe second switching control signal SWB (n) are set at a high level, andthe storage line capacitor CM included in the pixel circuit PC3 (x, n−1)and the pixel circuit PC3 (x, n) is reset by the reset transistor MRST1included in the pixel circuit PC3 (x, n−1).

After a specified elapsed time from time t1 when the read period TR (n)begins, when the second switching control signal SWB (n) and the secondswitching control signal SWB (n+1) change from a low level to a highlevel, each second switching transistor MSWB included in the pixelcircuit PC3 (x, n) and the pixel circuit PC3 (x, n+1) is set in aconductive state. As a result, in the pixel circuit PC3 (x, n) selectedin the read period TR (n), the floating diffusion capacitor CFD iscoupled in parallel to the storage line capacitor CM for three pixelcircuits PC3, via the first switching transistor MSWA and the secondswitching transistor MSWB.

Before time tHR, the floating diffusion capacitor CFD of the pixelcircuit PC3 (x, n) and each storage line capacitor CM of the pixelcircuit PC3 (x, n−1) to the pixel circuit PC3 (x, n+1) are reset andreleased from the reset by the reset transistor MRST1 of the pixelcircuit PC3 (x, n).

At time tHR, the programmable gain amplifier PGA included in the columncircuit 31 amplifies the signal inputted via the vertical signal lineVSL (x), and outputs a high-illuminance reset level as the PGA outputsignal POUT. Subsequently, at time tLR, time tLS, and time tHS, theprogrammable gain amplifier PGA outputs a low-illuminance reset level, alow-illuminance signal level, and a high-illuminance signal level,sequentially. During this period, the pixel circuit PC3 (x, n−1) to thepixel circuit PC3 (x, n+1) are coupled by the first switching transistorMSWA, as described above.

When the read of the high-illuminance signal level which has started attime tHS is completed, the first switching transistor MSWA and thesecond switching transistor MSWB of the pixel circuit PC3 (x, n) and thesecond switching transistor MSWB of the pixel circuit PC3 (x, n+1) aremaintained in a conductive state. In that state, the reset transistorMRST1 of the pixel circuit PC3 (x, n) is set in a conductive state andthe residual charge of the storage line capacitor CM of the pixelcircuit PC3 (x, n−1) to the pixel circuit PC3 (x, n+1) is discharged.

As is the case with the read period TR (n), in the read period TR (n+1)from time t2 to time t3, the first switching transistor MSWA included inthe pixel circuit PC3 (x, n+1) arranged at the selected (n+1) th row andthe first switching transistor MSWA included in the pixel circuit PC3(x, n+2) arranged at the non-selected (n+2)th row are set in aconductive state, accordingly, it becomes possible to couple in parallelthe capacitor CM of three unit storage capacitance lines USCL to thefloating diffusion capacitor CFD of the pixel circuit PC3 (x, n+1)arranged at the selected (n+1)th row.

In addition to the pixel circuit PC3 (x, n) arranged at the selected nthrow and the pixel circuit PC3 (x, n+1) arranged at the non-selected(n+1) th row, the second switching transistor MSWB included in the pixelcircuit PC3 (x, n+2) arranged at the non-selected (n+2)th row is set ina conductive state, accordingly, it becomes possible to couple inparallel the capacitor CM of five unit storage capacitance lines USCL tothe floating diffusion capacitor CFD of the pixel circuit PC3 arrangedat the selected row.

The effect of imaging device 300 according to Embodiment 3 is explained.In the imaging device 100 according to Embodiment 1, only the pixelcircuit PC1 arranged at the selected row is coupled to the storagecapacitance line SCL via the first switching transistor MSWA, and thepixel circuit PC1 arranged at other non-selected rows is electricallydisconnected from the storage capacitance line SCL. As a result, as forthe pixel circuit PC1 arranged at the selected row, the capacitor of thestorage line capacitor CM multiplied by the number of rows, that is, thecapacitor of the entire storage capacitance line SCL, is coupled inparallel to the floating diffusion CFD. On the other hand, in theimaging device 300, it is possible to select the number of the storageline capacitors CM coupled in parallel to the floating diffusioncapacitor CFD of the pixel circuit PC3. Consequently, it is possible tooptimize the number of the storage line capacitors CM which should becoupled to the floating diffusion capacitor, according to the number ofthe pixel circuits arranged in the column direction.

Embodiment 4

FIG. 14 is a block diagram illustrating a configuration of an imagingdevice 400 according to Embodiment 4.

In FIG. 14, an element to which the same symbol as in FIG. 11 isattached has the same configuration or the same function, and theduplicated explanation thereof will be omitted. The imaging device 400illustrated in FIG. 14 corresponds, in configuration, to the imagingdevice 300 illustrated in FIG. 11 in which a top reset transistor MRST_T(x) and a bottom reset transistor MRST_B (x) are added and the verticalscanning circuit 23 is replaced with a vertical scanning circuit 24. Inaddition to the row selection signal group R3 (n), the vertical scanningcircuit 24 outputs a reset signal RST_ALL which controls the conductivestate of the top reset transistor MRST_T (x) and the bottom resettransistor MRST_B (x).

The pixel array 14 is configured with a pixel circuit PC3, a verticalsignal line VSL, a storage capacitance line SCL, a top reset transistorMRST_T (x), and a bottom reset transistor MRST_B (x).

FIG. 15 is a circuit diagram illustrating the coupling relation of thepixel circuit PC3, the top reset transistor MRST_T (x), and the bottomreset transistor MRST_B (x), illustrated in FIG. 14.

The source of the second switching transistor MSWB included in the pixelcircuit PC3 (x, M) arranged at the top side (the opposite side of theside where the column circuit 31 is arranged) of the pixel array 14 iscoupled to a drain of the top reset transistor MRST_T (x). The powersupply voltage VDD is applied to a source of the top reset transistorMRST_T (x). The drain of the second switching transistor MSWB includedin the pixel circuit PC3 (x, 0) arranged at the bottom side (the sidewhere the column circuit 31 is arranged) of the pixel array 14 iscoupled to a drain of the bottom reset transistor MRST_B (x). The powersupply voltage VDD is applied to a source of the bottom reset transistorMRST_B (x). A reset signal RST_ALL outputted by the vertical scanningcircuit 24 is applied to a gate of the top reset transistor MRST_T (x)and to a gate of the bottom reset transistor MRST_B (x).

FIG. 16 is a timing chart explaining the read operation of the pixelcircuit PC3 illustrated in FIG. 15. The timing chart illustrated in FIG.16 is different from the timing chart illustrated in FIG. 13 in thefollowing points.

That is, in FIG. 13, when the read of the pixel circuit PC3 (x, n)arranged at the selected nth row is completed, the first switchingtransistor MSWA and the second switching transistor MSWB of the pixelcircuit PC3 (x, n) and the second switching transistor MSWB of the pixelcircuit PC3 (x, n+1) are maintained in a conductive state, up to timet2. During the period, the reset transistor MRST1 of the pixel circuitPC3 (x, n) set in a conductive state discharges the residual charge ofthe storage line capacitor CM from the pixel circuit PC3 (x, n−1) to thepixel circuit PC3 (x, n+1).

On the other hand, as illustrated in FIG. 16, in the read period TR (n),in addition to the above-described control of the pixel circuit PC3, thevertical scanning circuit 24 discharges the residual charge of thestorage line capacitor CM from the pixel circuit PC3 (x, n−1) to thepixel circuit PC3 (x, n+1), with the use of the top reset transistorMRST_T (x) and the bottom reset transistor MRST_B (x).

Immediately before time t2 when the read period TR (n) ends, a one shotpulse is generated in the reset signal RST_ALL, and at the same time,the one shot pulse is applied to the second switching control signal SWBincluded in the pixel circuit PC3 arranged at rows other than the pixelcircuit PC3 (x, n) of the nth row and the pixel circuit PC3 (x, n+1) ofthe (n+1)th row. Accordingly, the residual charge of the storage linecapacitor CM included in the each pixel circuit PC3 is discharged to thepower supply, also by the top reset transistor MRST_T (x) and the bottomreset transistor MRST_B (x).

The effect of imaging device 400 according to Embodiment 4 is asfollows. The residual charge of the storage line capacitor CM isdischarged quickly, and a high-speed operation is realized.

Embodiment 5

FIG. 17 is a block diagram illustrating a configuration of an imagingdevice 500 according to Embodiment 5.

In FIG. 17, an element to which the same symbol as in FIG. 14 isattached has the same configuration or the same function, and theduplicated explanation thereof will be omitted. The imaging device 500illustrated in FIG. 17 corresponds, in configuration, to the imagingdevice 400 illustrated in FIG. 14 in which the pixel circuit PC3 isreplaced with a pixel circuit PC5 and the vertical scanning circuit 24is replaced with a vertical scanning circuit 25.

The pixel array 15 is configured with a pixel circuit PC5, a verticalsignal line VSL, a storage capacitance line SCL, a top reset transistorMRST_T (x), and a bottom reset transistor MRST_B (x).

FIG. 18 is a circuit diagram illustrating the coupling relation of thepixel circuit PC5, the top reset transistor MRST_T (x), and the bottomreset transistor MRST_B (x), illustrated in FIG. 17.

The pixel circuit PC5 corresponds, in configuration, to the pixelcircuit PC3 illustrated in FIG. 15 in which the connection node of thedrain of the reset transistor MRST1 is changed from one end of thefloating diffusion capacitor CFD to the node at which one of the sourceand the drain of the first switching transistor MSWA and the source ofthe second switching transistor MSWB are coupled, and the symbol of thereset transistor MRST1 is changed to MRST2. Consequently, when resettingthe floating diffusion capacitor CFD by the reset transistor MRST2, thefirst switching transistor MSWA is also set in a conductive state.

The number of transistors included in the pixel circuit PC5 and thepixel circuit PC3 is the same. However, the number of transistorscoupled to the floating diffusion capacitor CFD is less by one in thepixel circuit PC5 than in the pixel circuit PC3. As a result, thefloating diffusion capacitor CFD of the pixel circuit PC5 decreases, incomparison with the pixel circuit PC3, by the amount of the parasiticcapacitance in the gate-source of the reset transistor MRST1;accordingly, the sensitivity at a low illuminance improves.

FIG. 19 is a timing chart explaining the read operation of the pixelcircuit PC5 illustrated in FIG. 18. The timing chart illustrated in FIG.19 is different from the timing chart illustrated in FIG. 16 in thefollowing points.

First, as illustrated in FIG. 16, when the read period TR (n) of thepixel circuit PC3 (x, n) ends, the vertical scanning circuit 24 sets thereset transistor control signal RST1 (n) at a high level, and resets thefloating diffusion capacitor CFD by the reset transistor MRST1. At thistime, it is necessary to set the first switching transistor MSWA in anon-conductive state, in order that the reset operation of the floatingdiffusion capacitor CFD may not be influenced by the potentialfluctuation of the unit storage capacitance line USCL.

In contrast with this, as illustrated in FIG. 19, the vertical scanningcircuit 25 maintains the high level of the first switching controlsignal SWA (n), in the next read period TR (n+1) and subsequent readperiods after the end of the read period TR (n). This is for the resettransistor MRST2 to reset the floating diffusion capacitor CFD via thefirst switching transistor MSWA.

Next, when the second switching transistor MSWB and the unit storagecapacitance line USCL are provided as in the pixel circuit PC5illustrated in FIG. 18, it is not desirable that the second switchingtransistor MSWB resets the unit storage capacitance line USCL of thepixel circuit PC5 (x, n) in a conductive state by the reset transistorMRST2. For example, as illustrated in FIG. 19, when reading the data ofthe pixel circuit PC (x, n) in the read period TR (n), the secondswitching transistor MSWB of the pixel circuit PC (x, n+1) is set in aconductive state. However, it is necessary to set the reset transistorMRST2 of the pixel circuit PC (x, n+1) in a non-conductive state. Thisis the reason why the reset control signal RST2 (n+1) is set at a lowlevel in the read period TR (n) in FIG. 19.

The effect of the imaging device 500 according to Embodiment 5 is asfollows. The value of the floating diffusion capacitor CFD decreases,and the sensitivity at a low illuminance improves.

Embodiment 6

FIG. 20 is a block diagram illustrating a configuration of an imagingdevice 600 according to Embodiment 6.

In FIG. 20, an element to which the same symbol as in FIG. 14 isattached has the same configuration or the same function, and theduplicated explanation thereof will be omitted. The imaging device 600illustrated in FIG. 20 corresponds, in configuration, to the imagingdevice 400 illustrated in FIG. 14 in which the pixel circuit PC3 isreplaced with a pixel circuit PC6 and the vertical scanning circuit 24is replaced with a vertical scanning circuit 26. The vertical scanningcircuit 26 controls the operation of the pixel circuit PC6 arranged atthe nth row by a row selection signal group R6 (n).

The pixel array 16 is configured with a pixel circuit PC6, a verticalsignal line VSL, a storage capacitance line SCL, a top reset transistorMRST_T (x), and a bottom reset transistor MRST_B (x). Differently fromthe pixel array provided in the imaging device according to otherembodiments, the pixel array 16 is configured with the pixel circuitsPC6 arranged in the shape of an array of (N+1) pieces in the rowdirection and (M+1)/2 pieces in the column direction. As will bedescribed later, the pixel circuit PC6 is provided with twophotoelectric conversion elements arranged in the column direction.Therefore, by arranging (M+1)/2 pieces of the pixel circuit PC6, Mpieces of the photoelectric conversion elements are arranged in thecolumn direction.

FIG. 21 is a circuit diagram of a pixel circuit PC6 illustrated in FIG.20.

(Configuration) The pixel circuit PC6 corresponds, in configuration, tothe pixel circuit PC3 illustrated in FIG. 12 in which a photoelectricconversion element PD2 and a transfer transistor MTX2 are added.

The pixel circuit PC6 is configured with photoelectric conversionelements PD1 and PD2, transfer transistors MTX1 and MTX2, a floatingdiffusion capacitor CFD, a reset transistor MRST1, an amplificationtransistor MAMI, a select transistor MSEL, a first switching transistorMSWA, a second switching transistor MSWB, and a storage line capacitanceCM.

The power supply voltage GND is applied to an anode of each of thephotoelectric conversion elements PD1 and PD2. A cathode of each of thephotoelectric conversion elements PD1 and PD2 is coupled to one of asource and a drain of each of the transfer transistors MTX1 and MTX2,respectively. The other of the source and the drain of each of thetransfer transistors MTX1 and MTX2 is coupled to one end of the floatingdiffusion capacitor CFD. The power supply voltage GND is applied to theother end of the floating diffusion capacitor CFD. A drain of the resettransistor MRST1 is coupled to the one end of the floating diffusioncapacitor CFD. The power supply voltage VDD is applied to a source ofthe reset transistor MRST1.

The power supply voltage VDD is applied to a source of the amplificationtransistor MAMI and the voltage of the one end of the floating diffusioncapacitor CFD is applied to a gate of the amplification transistor MAMI.A drain of the amplification transistor MAMI is coupled to a source ofthe select transistor MSEL, and a drain of the select transistor MSEL iscoupled to the vertical signal line VSL. One of a source and a drain ofthe first switching transistor MSWA is coupled to the one end of thefloating diffusion capacitor CFD. The other of the source and the drainof the first switching transistor MSWA is coupled to the unit storagecapacitance line USCL. One end of the unit storage capacitance line USCLis coupled to a source of the second switching transistor MSWB, and theother end is coupled to a drain of a second switching transistor MSWBincluded in the pixel circuit PC6 arranged adjacently.

The storage line capacitor CM corresponds to the wiring capacitance ofthe unit storage capacitance line USCL. The unit storage capacitanceline USCL corresponds to a portion of the storage capacitance line SCL(x) which is included in the pixel circuit PC6 (x, n).

A transfer transistor control signal TX1, a transfer transistor controlsignal TX2, a reset transistor control signal RST1, a select transistorcontrol signal SEL, a first switching control signal SWA, and a secondswitching control signal SWB are applied to the respective gates of thetransfer transistor MTX1, the transfer transistor MTX2, the resettransistor MRST1, the select transistor MSEL, the first switchingtransistor MSWA, and the second switching transistor MSWB. The rowselection signal group R6 (n) is a bunch of these six control signals.

(Operation) The outline of operation of the pixel circuit PC6 controlledby the vertical scanning circuit 26 is as follows. In the followingexplanation, it is assumed that the storage line capacitor CM is thecapacitor of three unit storage capacitance lines USCL (refer toEmbodiment 3). When the pixel circuit PC6 arranged in the nth row isselected by the vertical scanning circuit 26, the floating diffusioncapacitor CFD and the storage line capacitor CM coupled in parallel bythe first switching transistor MSWA are reset by the reset transistorMRST1. The amplification transistor MAMI amplifies the voltage of thefloating diffusion capacitor CFD, and based on the amplified voltage,the column circuit 31 generates a high-illuminance digital reset signal.

Subsequently, the floating diffusion capacitor CFD is separated from thestorage line capacitor CM by the first switching transistor MSWA. Theamplification transistor MAMI amplifies the voltage of the floatingdiffusion capacitor CFD, and based on the amplified voltage, the columncircuit 31 outputs a low-illuminance digital reset signal.

Subsequently, the photo charge stored in the photoelectric conversionelement PD1 is transferred to the floating diffusion capacitor CFD viathe transfer transistor MTX1. A charge overflowing from the floatingdiffusion capacitor CFD is stored in the storage line capacitor CM. Theamplification transistor MAMI amplifies the voltage of the floatingdiffusion capacitor CFD, and based on the amplified voltage, the columncircuit 31 generates a low-illuminance digital signal.

Subsequently, the first switching transistor MSWA is set in a conductivestate, and the floating diffusion capacitor CFD and the storage linecapacitor CM are coupled in parallel. The amplification transistor MAMIamplifies the voltage of the floating diffusion capacitor CFD, and basedon the amplified voltage, the column circuit 31 generates ahigh-illuminance digital signal.

When the generation of the high-illuminance digital reset signal, thelow-illuminance digital reset signal, the low-illuminance digitalsignal, and the high-illuminance digital signal, based on the photocharge stored in the photoelectric conversion element PD1 is completed,the vertical scanning circuit 26 generates succeedingly each of thedigital signals, based on the photo charge stored in the photoelectricconversion element PD2.

FIG. 22 is a layout pattern of the pixel circuit PC6 illustrated in FIG.21. FIG. 22 is the layout pattern of a total of four pixel circuits PC6,arranged at the (x−1) th column and the xth column of the nth row, andat the (x−1) th column and the xth column of the (n−2) th row. Thearrangement of a transistor, etc. in the pixel circuit PC6 (x, n)arranged at the upper right is explained among the four pixel circuitsPC6, as an example.

(An intra-row area and an inter-row area) The photoelectric conversionelement PD1 and the photoelectric conversion element PD2 are arranged inthe column direction. The photoelectric conversion element PD1, forexample, is a pn junction diode which is formed with an n-type impurityarea formed in a p-well area of a semiconductor substrate, and ahigh-concentration p-type impurity region formed over the n-typeimpurity area (not shown). In the neighborhood of the photoelectricconversion element PD1 or the photoelectric conversion element PD2, awell contact WCNT for supplying the power supply voltage GND to thep-well area is arranged.

In the area between the photoelectric conversion element PD1 and thephotoelectric conversion element PD2 arranged in the same row (the areamay be described as an “intra-row area” hereinafter), the transfertransistor MTX1, the transfer transistor MTX2, the floating diffusionFD, the reset transistor MRST1, the amplification transistor MAMI, thefirst switching transistor MSWA, and the floating diffusion wiring FDLare formed. On the other hand, in the area between the photoelectricconversion element PD1 and the photoelectric conversion element PD2arranged at different rows (the area may be described as an “inter-rowarea” hereinafter), the select transistor MSEL, the second switchingtransistor MSWB, and the well contact WCNT are arranged.

(Separate arrangement of the amplification transistor MAMI and theselect transistor MSEL) In the pixel circuit PC6 (x, n), the formingregion of the amplification transistor MAMI and the forming region ofthe select transistor MSEL are separated. The amplification transistorMAMI is arranged in the intra-row area and the select transistor MSEL isarranged in the inter-row area. The drain region of the amplificationtransistor MAMI and the source region of the select transistor MSEL arecoupled by an intermediate connection line INTW. The drain of the selecttransistor MSEL is coupled to the vertical signal line VSL (x).

In the inter-row area adjoining the photoelectric conversion elementPD2, the second switching transistor MSWB included in the pixel circuitPC6 (x, n+2) is arranged. In the inter-row area adjoining thephotoelectric conversion element PD1, the second switching transistorMSWB included in the pixel circuit PC6 (x, n) is arranged. The wiringwhich couples both second switching transistors MSWB is the unit storagecapacitance line USCL. The unit storage capacitance line USCL is coupledto one of the source and the drain of the first switching transistorMSWA. By separately arranging the forming region of the amplificationtransistor MAMI and the select transistor MSEL, it becomes possible toutilize effectively the intra-row area and the inter-row area.

(The configuration of the transfer transistors MTX1/MTX2) The gateelectrodes of the transfer transistor MTX1 and the transfer transistorMTX2 are arranged in the intra-row area, respectively lying along thephotoelectric conversion element PD1 and the photoelectric conversionelement PD2 and facing with each other. Between the gate electrodes ofthe transfer transistor MTX1 and the transfer transistor MTX2, thesource and drain region of both the transfer transistors are formedhaving a width narrower enough than the width of each gate electrode. Asthe result of having arranged the select transistor MSEL in theinter-row area, it becomes possible to set up more widely the gate widthof the transfer transistor MTX1 and the transfer transistor MTX2arranged in the intra-row area. Accordingly, the driving ability of thetransfer transistor MTX1 and the transfer transistor MTX2 isstrengthened, and the velocity to transfer the photo charge from thephotoelectric conversion element PD1 and the photoelectric conversionelement PD2 to the floating diffusion capacitor CFD is enhanced.

(The configuration of the floating diffusion) When arranged between thegate electrodes of the transfer transistor MTX1 and the transfertransistor MTX2, the width of the source and drain region of both thetransfer transistors can be set as minimum necessary and smaller thanthe width of each gate electrode. On the other hand, the resettransistor MRST1 is arranged between the transfer transistors MTX1 andMTX2 and the amplification transistor MAMI. Sandwiching the transfertransistors MTX1 and MTX2, the first switching transistor MSWA isarranged on the opposite side of the reset transistor MRST1.

The drain region of the reset transistor MRST1 and one of the source anddrain region of the first switching transistor MSWA are coupled to oneof the source and drain region of the transfer transistor MTX1 andtransfer transistor MTX2, by an impurity diffusion region set as thenecessary minimum width. As a result, it is possible to suppress, to theminimum necessary value, the parasitic capacitance which stems from thesource or drain region of the transfer transistor MTX1, the transfertransistor MTX2, the reset transistor MRST1, and the first switchingtransistor MSWA, and which is included in the floating diffusioncapacitor CFD. As a result, it becomes possible to improve thesensitivity of the pixel circuit PC6 in the low illuminance side.

It should be understood by those skilled in the art that the embodimentsdisclosed in the present application are illustrative and notrestrictive, with all the points of view. The scope of the presentinvention is illustrated not by the explanatory description given abovebut by the scope of the appended claims, and it is meant that variousmodifications and alterations may occur insofar as they are within thescope of the appended claims or the equivalents thereof.

What is claimed is:
 1. An imaging device, comprising: a plurality ofpixel circuits arranged in the row direction and the column direction;and a plurality of storage capacitance lines arranged in the rowdirection and extending in the column direction, wherein the storagecapacitance lines are coupled to the pixel circuits arranged in the samecolumn, wherein the pixel circuits each comprise: a first photoelectricconversion element operable to store a charge generated by beingsubjected to light; a floating diffusion to which the charge stored inthe first photoelectric conversion element is transferred; a firstswitching transistor operable to couple the floating diffusion and thestorage capacitance line; and a first reset transistor with a sourcecoupled to a power supply line and a drain coupled to the storagecapacitance line; wherein the first reset transistor performs resettingto discharge a charge stored in at least one of the floating diffusionand the storage capacitance line, wherein, in a selected row where afirst pixel circuit, of the plurality of pixel circuits, with a selecttransistor set in a conductive state is arranged, the first switchingtransistor of the first pixel circuit is set in a conductive state,wherein, in a non-selected row where a second pixel circuit, of theplurality of pixel circuits, with a select transistor set in anon-conductive state is arranged, the first switching transistor of thesecond pixel circuit is set in a non-conductive state, and wherein thepixel circuit further comprises: a second photoelectric conversionelement operable to store a charge generated by being subjected tolight; a first transfer transistor operable to transfer a charge storedin the first photoelectric conversion element to the floating diffusion;and a second transfer transistor operable to transfer a charge stored inthe second photoelectric conversion element to the floating diffusion.2. An imaging device, comprising: a plurality of pixel circuits arrangedin the row direction and the column direction; and a plurality ofstorage capacitance lines arranged in the row direction and extending inthe column direction, wherein the storage capacitance lines are coupledto the pixel circuits arranged in the same column, wherein the pixelcircuits each comprise: a first photoelectric conversion elementoperable to store a charge generated by being subjected to light; afloating diffusion to which the charge stored in the first photoelectricconversion element is transferred; a first switching transistor operableto couple the floating diffusion and the storage capacitance line; and afirst reset transistor with a source coupled to a power supply line anda drain coupled to the storage capacitance line; wherein the first resettransistor performs resetting to discharge a charge stored in at leastone of the floating diffusion and the storage capacitance line, wherein,in a selected row where a first pixel circuit, of the plurality of pixelcircuits, with a select transistor set in a conductive state isarranged, the first switching transistor of the first pixel circuit isset in a conductive state, wherein, in a non-selected row where a secondpixel circuit, of the plurality of pixel circuits, with a selecttransistor set in a non-conductive state is arranged, the firstswitching transistor of the second pixel circuit is set in anon-conductive state, and wherein the storage capacitance line isconfigured with a plurality of unit storage capacitance lines arrangedin the column direction, wherein the pixel circuit further comprises asecond switching transistor, wherein the first switching transistorcouples the floating diffusion to the unit storage capacitance line, andwherein the second switching transistor couples the unit storagecapacitance lines in series.
 3. The imaging device according to claim 2,wherein in the pixel circuit arranged at the selected row and in thepixel circuit arranged at the non-selected row adjoining the selectedrow, the second switching transistor is set in a conductive state. 4.The imaging device according to claim 2, further comprising a thirdreset transistor, wherein: the third reset transistor is coupled to theunit storage capacitance line arranged at the end of the columndirection, and performs resetting to discharge a charge stored in theunit storage capacitance lines arranged in the column direction.
 5. Animaging device, comprising: a plurality of pixel circuits arranged inthe row direction and the column direction; a plurality of storagecapacitance lines arranged in the row direction and extending in thecolumn direction; and a plurality of vertical signal lines arranged inthe row direction and extending in the column direction, wherein thestorage capacitance lines are coupled to the pixel circuits arranged inthe same column, wherein the pixel circuits each comprise: a firstphotoelectric conversion element operable to store a charge generated bybeing subjected to light; a floating diffusion to which the chargestored in the first photoelectric conversion element is transferred; afirst switching transistor operable to couple the floating diffusion andthe storage capacitance line; a first reset transistor with a sourcecoupled to a power supply line and a drain coupled to the storagecapacitance line; an amplification transistor operable to amplify andoutput a voltage of the floating diffusion; and a select transistoroperable to couple the amplification transistor to the vertical signalline; wherein the vertical signal line is coupled to the pixel circuitsarranged in the same column, wherein to the vertical signal line, theamplification transistor: outputs a high-illuminance reset noise byamplifying a voltage of the floating diffusion to which resetting hasbeen performed together with the storage capacitance line; outputs alow-illuminance reset noise by amplifying a voltage of the floatingdiffusion separated from the storage capacitance line after theresetting; subsequently, outputs a low-illuminance mixed signal byamplifying a voltage of the floating diffusion to which a charge storedin the first photoelectric conversion element is transferred; andsubsequently, outputs a high-illuminance mixed signal by amplifying avoltage of the floating diffusion coupled to the storage capacitanceline.
 6. The imaging device according to claim 5, further comprising: aplurality of column circuits arranged in the row direction, wherein: thecolumn circuit is coupled to a vertical signal line arranged in the samecolumn, and the column circuit outputs a high-illuminance digital resetsignal by performing digital conversion to the high-illuminance resetnoise outputted by the vertical signal line, the column circuit outputsa low-illuminance digital reset signal by performing digital conversionto the low-illuminance reset noise outputted by the vertical signalline, the column circuit outputs a low-illuminance digital signal byperforming digital conversion to the low-illuminance mixed signaloutputted by the vertical signal line, and the column circuit outputs ahigh-illuminance digital signal by performing digital conversion to thehigh-illuminance mixed signal outputted by the vertical signal line. 7.The imaging device according to claim 5, further comprising a pluralityof first column circuits and a plurality of second column circuits,respectively arranged in the row direction, wherein the vertical signalline is coupled to the first column circuit and the second columncircuit, each arranged in the same column, the first column circuit isprovided with a first switch, a first amplifier, and a firstanalog-to-digital converter, the second column circuit is provided witha second switch, a second amplifier, and a second analog-to-digitalconverter, the first amplifier and the second amplifier amplifyrespectively the low-illuminance mixed signal and the high-illuminancemixed signal, both outputted by the vertical signal line, and output alow-illuminance signal level and a high-illuminance signal level,sequentially, and the first analog-to-digital converter and the secondanalog-to-digital converter convert in parallel the low-illuminancesignal level and the high-illuminance signal level into alow-illuminance digital signal and a high-illuminance digital signal,respectively.